The present invention relates to electric devices, and more particularly to memories and amplifiers.
The popularity of battery-powered electronic devices such as laptop, notebook, sub-notebook and hand-held computers increased the need for circuitry that operates efficiently at lower power supply voltages. A typical laptop computer is powered by a 3.0 V power supply as compared to 5.0 V power supplies used in some older non-portable computers. Older memories and sense amplifiers developed for use with the 5.0 V power supplies are often inadequate for use with lower voltage power supplies as illustrated by the following example.
FIG. 1 is a circuit diagram of one column of an array of four-transistor memory cells of a prior art static random access memory ("SRAM"). Such a memory is described in the aforementioned U.S. patent application Ser. No. 07/709,924. For simplicity, only two memory cells 110A and 110B are shown in FIG. 1, and only the cell 110A is shown in detail. Memory cell 110A includes pull-down transistors 116, 122, pass transistors 130, 134, and load resistors 136, 138. The memory cell is powered by voltage VCC=5.0 V. Voltage VSS is ground (0.0 V). The voltages at nodes N, N at the drains of respective pull-down transistors 116, 122 determine the state of the memory cell (binary 0 or 1). In one state, the voltage at node N is high (near VCC) and the voltage at node N is low (near 0.0 V). i In the other state, node N is high and node N is low.
When memory cell 110A is being read, word line WL-A is driven high to turn on pass transistors 130, 134 and thereby to connect nodes N, N to respective bit lines BL, BL. Line 140 is driven high to turn on Y-decode transistors 142, 144 and thus to connect bit lines BL, BL to respective inputs 150a, 150b of sense amplifier 150. Sense amplifier 150 tracks the bit line voltages. Word line WL-A and line 140 remain high during tracking. Sense amplifier 150 produces on output lead 170 a signal indicative of the difference between the voltages on bit lines BL, BL and hence indicative of the state of memory cell 110A.
Equalizing transistor 180 resistively shorts bit lines BL and BL to each other to prevent the difference between the bit line voltages from exceeding a predetermined value, 0.3 V in some embodiments. This is done to prevent accidental toggling (and hence overwriting) of the memory cells as explained more fully in the aforementioned patent application Ser. No. 07/709,924.
Bit lines BL, BL are charged statically by respective transistors 172, 174. Between reading operations, transistors 172 and 174 bias the respective bit lines at about VCC/2=2.5 V. When memory cell 110A is being read, transistors 172, 174 remain on preventing the bit line voltages from decreasing below a predetermined value, 2.2 V in some embodiments. This is done to prevent accidental toggling of the memory cell. Namely, during reading, the memory cell pulls down both bit lines BL and BL and not only the bit line connected to the low voltage node N or N, because equalizing transistor 180 resistively shorts the bit lines as described above. In addition, both bit lines are pulled down by charge leakage. If the voltages on both bit lines become low, below 2.2 V in some embodiments, the conductance of pull-down transistors 116, 122 becomes so low that the memory cell may toggle (i.e. switch states). By remaining on during reading, transistors 172, 174 prevent such toggling. Between reading operations, transistors 172, 174 keep the bit lines at 2.5 V in order to ensure the 2.5 V bit line voltage at the start of each reading operation and thus to prevent a low voltage caused by the previous operation or by the charge leakage from toggling a memory cell.
FIG. 2 is a circuit diagram of sense amplifier 150 which is powered by voltage VCC=5.0 V. Matched pull-up PMOS transistors 202, 203, connected as a current mirror, provide current to respective nodes 204, 205. Matched pull-down NMOS transistors 206, 207 sink current from respective nodes 204, 205. NMOS transistor 208, whose gate is connected to a constant voltage VREF, is a current source which sets the total current passing through transistors 206, 207.
Inputs 150a, 150b of amplifier 150 are connected to the gates of respective transistors 206, 207 so as to control the currents through the transistors. The balance of the currents through transistors 206, 207 determines the output voltage DOUT on the output lead 170 which is connected to node 205. If inputs 150a, 150b are at equal voltages, the currents through transistors 206, 207 are equal, and the voltages at nodes 204, 205 are also equal. If the voltage on input 150a is higher than the voltage on input 150b, transistor 206 sinks more current than transistor 207. The voltage on node 204 goes down, the voltage on node 205 goes up, and increased DOUT indicates that the voltage on input 150a is above the voltage on input 150b.
Similarly, if input 150a is lower than input 150b, transistor 207 sinks more current than transistor 206. Node 205 is pulled down, and decreased DOUT indicates that the voltage on input 150b is above the voltage on input 150a.
If VCC is reduced to 3.0 V as in laptop computers, the currents through transistors 206, 207 decrease, and sense amplifier 150 becomes slower since it takes longer to pull down node 204 or 205. The speed of the sense amplifier could be increased by increasing the power consumption, but increased power consumption is undesirable in general and especially so in battery-powered laptop computers.
Further, as is known in the art, transistors 206, 207 must be in saturation to maximize the gain of the sense amplifier. The saturation requirement restricts the range of permissible voltages on inputs 150a, 150b. When VCC decreases to 3.0 V, the range of permissible voltages becomes restricted further. The difference between the currents at nodes 204, 205 becomes therefore smaller, and the sense amplifier becomes slower because it takes longer to transform the smaller current difference into an output level DOUT indicative of the state of the memory cell. Further, the smaller difference between the voltages on inputs 150a, 150b is easier to upset by noise and by temperature and process variations. In particular, temperature and process variations may affect the memory so as to further reduce the difference between the voltages on inputs 150a, 105b causing the voltage difference to be unnoticeable to sense amplifier 150 at VCC=3.0 V. Process variations may also affect sense amplifier 150 by, for example, causing a mismatch of transistors 206, 207 so that sense amplifier 150 would pull down a wrong one of nodes 204, 205 when the voltage difference between inputs 150a, 150b is small as it is at VCC=3.0 V. Thus the noise immunity of the sense amplifier and the tolerance to temperature and process variations are inadequate for 3.0 V power supply systems.
There is a need therefore for faster and more power-efficient memories and sense amplifiers which have improved noise immunity and improved tolerance to temperature and process variations and which can operate at low power supply voltages such as used in laptop, notebook, sub-notebook and hand-held computers.